1. Field of the Invention
This invention proposes a high margin precision manufacturing method for a self-aligned contact. More specifically, this invention relates to a manufacturing process for a self-aligned contact in which a hard mask layer and a polysilicon spacer are formed so as to increase the margin and precision of self-aligned etching. Therefore, the misalignment problem derived from the increasing density of the transistor devices can be overcome.
2. Description of the Prior Art
The area of a MOS device is increasingly reduced in synchronization with the development of the semiconductor integrated circuit. Although reduction of the length of the gate electrode improves the performance and the speed of processor or dynamic random access memory (DRAM), the RC (i.e., resistor times capacitor) delay time of the conductive connection becomes longer. The transfer time of the gate electrode is far larger than the RC delay time of conductive connection before the micron devices are developed. With the development of VLSI, the transfer time of the gate electrode is approximately equal to the RC delay time of conductive connection. Therefore, the application of the multi-layered conductive line to reduce the length of the conductive line is unavoidable, and hence the resistance is reduced. This goal is easily achieved while the line width is far larger than the thickness of metal film. However, it is impossible to achieve this goal without developing other manufacturing processes when line width with a micron grade is developed.
DRAM is a major volatile memory. Because the integration requirement of the semiconductor devices is increasingly higher, the combination of logic and DRAM is widely applied to wafers, and the bit-line contact and the node contact are both designed to be self-aligned contacts (SAC) so as to reduce the size of the wafer.
Because of the shrinkage of the size and line width of MOS and metal line, portions of the metal line may contact the shallow trench isolation (STI) when the size of the source or drain region is smaller than the width of metal line, or when the misalignment occurs between source region or drain region and metal line.
By utilizing the conventional method of manufacturing the contact, the number of problems to be overcome is increased accompanied by the increased integration of the transistor devices. These problems occur easily and are illustrated in FIGS. 1 and 2. As shown in FIG. 1, a silicon substrate 10 is first provided, the silicon substrate 10 includes a metal-oxide semiconductor (MOS) structure formed thereon, wherein the MOS structure is composed of a gate electrode 14 and a source/drain region 12. The gate (electrode 14 is further composed of a polysilicon layer 16, a silicide layer 18, and silicon nitride layer 20, and a gate spacer 22 is formed on the sidewall of the gate electrode 14. Since the circuit integration is increased, the aspect ratio is increased accompanied by the reduction of contact size. Because the covering rate of the contact bottom is decreased, the inter-poly dielectric layer 24 cannot entirely fill the contact gaps and a void 26 is unavoidably formed in the contact and the subsequent processes are affected. In addition, the increasing of the devices integration also results in the misalignment a contact, as shown in FIG. 2, and a short circuit phenomenon therefore is produced due to the over-etching in the etch margin.